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as4c 64 m 16d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 1 rev. 1.1 april. /2012 1gb ( 64 m x 1 6 bi t ) ddri i synchronou s dra m (sdram) alliance memory confidentia l advanced (rev. 1.0 april 2012 ) features ? jedec standard compliant ? jedec standard 1.8v i/o (sstl_18 - compatible) ? power supplies: v dd & v ddq = +1 . 8v 0.1v ? operating tempera ture: - commercial (0 ~ 8 5c) - industrial ( - 40 ~ 95c) ? supports jedec clock jitter specification ? fully synchronous operation ? fast clock rate: 400 mhz ? differentia l clock , c k & ck# ? bidirectional single/differential data strobe - dq s & dqs# ? 8 internal banks f or concurrent operation ? 4 - bit prefetch architecture ? internal pipeline architecture ? precharge & active power down ? programmable mode & extended mode registers ? poste d cas # additiv e latenc y (al) : 0 , 1 , 2 , 3 , 4 , 5 , 6 ? write latency = read latency - 1 t ck ? burst l engths: 4 or 8 ? burs t type : sequentia l / interleave ? dll enable/disable ? on - die termination (odt) ? rohs compliant ? auto refresh and self refresh ? 8192 refresh cycles / 64ms - average refresh period 7. 8 s @ 0 Q t c Q +85 3. 9 s @ +85 t c Q +95 ? 84 - bal l 8 x 12. 5 x 1.2m m (max ) fbg a package - pb and halogen free overview the as4c64m16d2 is a high - speed cmos double - data - rate - two (ddr2), synchronous dynamic random - access memory (sdram) containing 1024 mbits in a 16 - bit wide data i/os. it is internally configured as a 8 - bank dram, 8 banks x 8mb addresses x 16 i/os. the device is designed to comply with ddr2 dram key features such as posted cas # wit h additiv e latency, write latency = read latency - 1 and on die ter mination(odt) . all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck# falling) all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs#) in a source synchronous fashion. the address bus is used to convey row, column, and bank address information in ras #, cas# mul t iple xi ng s tyl e. a ccesses begin with the registration of a bank activate command, and then i t is followed by a read or write command. read and write accesses to the ddr2 sdram are 4 or 8 - bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. an auto precharge function may be enabled to provide a self - timed row precharge that i s initiate d a t th e en d of the burst sequenc e. a sequential and gapless data rate is possible depending on burst length, cas latency, and speed grade of the device. table 1. ordering information par t number clock frequency data rate po w er supply package as4c64m16d2 - 25bcn 400mhz 800mbps/pin v dd 1 .8v , v dd q 1.8v fbga as4c64m16d2 - 25bin 400mhz 800mbps/pin vdd 1.8v, vddq 1.8v fbga b: indicates 84 - ball (8.0 x 12.5 x 1.2mm) fbga package c: indicates commercial temperature i: indicates industrial temperature n: indicates pb and halogen free rohs tabl e 2. speed grade information spee d grade clock frequency cas latency t rcd (ns) t rp (ns) ddr2 - 800 400 mhz 5 12.5 12.5
as4c 64 m 16d2 alliance memory inc . 551 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice. 2 rev. 1.1 april. /2012 figure 1> ball assignment (fbga top view)
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 3 rev. 1.1 april. /20 12
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 4 rev. 1.1 april. /20 12 figure 3. state diagram note: use caution with this d iagram. it is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. in particular situations involving more than one bank, enabling/disabling on - die termination, power down entry/exit, timing restrictions during state transitions, among other things, are not captured in full detail.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 5 rev. 1.1 april. /20 12 table 1 . ball descriptions s y mbol t y pe description ck , ck# input differential clock: ck, ck# are driven by the system clock. all sdram input sign als are sampled on the crossing of positive edge of ck and negative edge of ck#. output (read) data is referenced to the crossings of ck and ck# (both directions of crossing). cke input cloc k enable : cke activates (high) and deactivates (low) the ck signa l. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba0 - ba2 input bank address: ba0 - ba2 define to which bank the bankactivate , read , write , or bankprecharge command is being applied. a0 - a12 input address inputs: a0 - a12 are sampled during the bankactivat e command (row address a0 - a12) and read/write command (column address a0 - a9 with a 10 defining auto precharge). cs# input chi p select : cs# enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled hi gh. cs# provides for external bank selection on sys t ems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latch ed at the crossing of positive edges of ck and negative edge of ck#. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high," the bankactivate command is selected and the bank designated by ba is turned on to the active state. when the we# i s asserted "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the precharge operation . cas# input column address strobe: the cas# signal defines the operation commands in conjunction with the ras# and we# signals and is latched at the crossing of positive edges of ck and negative edge of ck#. when ras# is held "high" and cs# i s asserted " low," the column access is started by asserting cas# "low." then, the read or write command is selected by asserting we# high " or low". we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the crossing of positive edges of ck and negative edge of ck#. the we# i nput is used to select the bankactivate or precharge command and read or write command. ldqs, inpu t / bidirectional data strobe: specifies timing for input and outpu t data. read data ldqs# output strobe is edge triggered. write data strobe provides a setup and hold time for data and dqm. ldqs is for dq0~7, udqs is for dq8~15. the data strobes ldos and udqs udqs may be used in single ended mode or paired with ldqs # and udqs# to udqs# provide differential pair signaling to the s y stem during both reads and writes.a control bit at emr (1)[a10] enables or disables all complementary data strobe signals. ldm, udm input data input mask: input data is masked when dm is sampled high during a write c y cle. ldm masks dq0 - dq7, udm masks dq8 - dq15. dq0 - dq15 input / output data i/o: the data bus input and output data are synchronized with positive and negativ e edge s o f dqs/dqs# . th e i/o s a r e byte - maskable during writes.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 6 rev. 1.1 april. /20 12 odt input on die termination: odt enables internal termination resistance. it is applied to each dq, ldqs/ldqs#, udqs/udqs#, ldm, and udm signal. the odt pin is ignored if the emr (1) is programmed to disable odt. v dd supply po w er suppl y : +1 .8 v 0.1v v ss supply ground v ddl supply dl l po w er suppl y : +1 .8 v 0.1v v ssdl supply dll ground v ddq supply dq po w er: +1 . 8v 0.1v. v ssq supply dq ground v ref supply reference voltage for inputs: +0 .5*v ddq nc - no connect: these pins should be left unconnected.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 7 rev. 1.1 april. /20 12 operation mode table 4 shows the truth table for the operation commands. table 2 . truth table (note (1), (2)) co mm and state ck e n - 1 ck e n dm ba 0 - 2 a 10 a 0 - 9 , 11 - 12 cs# ras# cas# we# ban k a c tivate idl e (3) h h x v row address l l h h single bank precharge an y h h x v l x l l h l all banks precharge any h h x x h x l l h l write a c tiv e (3) h h x v l column address (a0 C a9) l h l l writ e wit h autopre c harge a c tiv e (3) h h x v h l h l l read activ e (3) h h x v l column address (a0 C a9) l h l h read and autop recharge activ e (3) h h x v h l h l h (extended) mode register set idle h h x v op code l l l l no - operation any h x x x x x l h h h bur st stop a c tiv e (4) h x x x x x l h h l devi ce de se le ct any h x x x x x h x x x refresh idle h h x x x x l l l h sel frefresh entry idle h l x x x x l l l h selfrefre sh exit idle l h x x x x h x x x l h h h power down mode entry idle h l x x x x h x x x l h h h powe r dow n mod e exit any l h x x x x h x x x l h h h dat a inpu t mas k disable active h x l x x x x x x x dat a inpu t mas k enable(5) active h x h x x x x x x x not e 1 : v=vali d data , x=don' t car e , l=lo w level , h=hig h level not e 2 : cken signal is input level when commands are provided. not e 3 : cke n - 1 signal is inp ut level one clock cyc l e before the commands are provided. not e 4 : these are states of bank designated by ba signal. not e 5 : device state is 4, and 8 burst operation. not e 6 : ldm and udm can be enabled respectively.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 8 rev. 1.1 april. /20 12 functional description read and write a ccesses to the ddr2 sdram are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. accesses begin w i th the registration of an active command, which is then followed by a read or wr i te command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0 - ba2 select the bank; a0 - a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determ i ne if the auto precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device i nitialization, register defi n ition, command descriptions, and device operation. ? po w e r - up and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. appl y powe r an d attemp t t o maintai n ck e belo w 0.2* v ddq and odt * 1 at a low state (all other inputs may be undefined.) the v dd voltage ramp time must be no greater than 200ms from when v dd ramps from 300mv to v dd min; and during the v dd voltag e ramp , | v dd - v ddq | Q 0.3v - v dd , v ddl and v ddq are driven from a single power converter output, and - v t t i s limite d t o 0.9 5 v max , and - v ref t racks v ddq /2. or - appl y v dd befor e o r a t th e sam e t im e a s v dd l . - appl y v ddl befor e o r a t th e sam e tim e a s v ddq . - appl y v ddq befor e o r a t th e sam e tim e a s v t t & v ref . a t leas t on e o f thes e tw o set s o f condition s mus t b e met. 2. start clock and maintain stable condition. 3. for the minimum of 20 0 s after stable powe r and clock (ck, ck#), then apply nop or deselect and take cke high. 4. wait minimum of 400ns then issue precharge all command. nop or deselect applied during 400ns period. 5. issue emrs(2) command. (to issue emrs (2) com m and , provid e low t o ba 0 an d ba2 , high t o ba1.) 6. issue emrs (3) command. (to issue emrs (3) com m and , provid e low t o ba2 , high t o ba 0 an d ba1.) 7. issue emrs to enable dll. (to issue "dll enable" command , provid e "low " t o a0 , "high " t o ba 0 and "low " t o ba 1 an d ba2.) 8. issue a mode register set c ommand for dll reset. (to issue dll reset command, provide "high" to a8 and "low" to ba0 - ba2) 9. issue precharge all command. 10. issue 2 or more auto - refresh commands. 11. issue a mode register set command with low to a8 to initialize device operation. (i.e. to pr ogram operating parameters without resetting the dll.) 12. at least 200 clocks after step 8, execute ocd calibration (off chip driver impedance adjustment).if ocd calibration is not used, emrs ocd default command (a9=a8=a7=high) followed by emrs ocd calibratio n m o d e exit command (a9=a8=a7=low) must be issued with other operating parameters of emrs. 13. the ddr2 sdram is now ready for normal operation. not e 1 : t o guarante e od t off , v r ef mus t b e vali d an d a lo w leve l mus t b e applie d t o th e od t pin.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 9 rev. 1.1 april. /2012 ? mode register se t(mrs) the mode register stores the data f o r controlling the various operating modes of ddr2 sdram. it controls cas latency, burst length, burst sequence, test mode, dll reset, wr, and various vendor specific options to make ddr2 sdram useful for various a pplications.the default v a lue of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. the mode register is written by assertin g lo w o n cs# , ras# , cas# , we# , ba 0 an d ba1 , w hile controll ing the state of address pins a0 - a12. the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the mode register.the mode register set command cycle time ( t m rd ) is required to complete the write operation to the mo de register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all bank are in the precharge state.the mode register is divide d int o variou s field s dependin g o n functionality. - b urst length field (a2, a1, a0) this field specifies the data length of column access and selects the burst length. - addressing mode select field (a3) the addressing mode can be interleave mode or s equentia l mode . bot h sequentia l mod e an d interleave mode sup port burst length of 4 and 8. - ca s latenc y fiel d (a6 , a5 , a4) this field specifies the number of clock cycles from the assertion of the read command to the first read data . th e minimu m whol e valu e o f ca s latenc y depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) Q ca s latenc y x t ck - tes t mod e field : a7 ; dl l rese t mod e field : a8 these two bits must be programmed to "00" in normal operation. - (ba0 - ba1): bank addresses to define mrs selectio n .
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 10 rev. 1.1 april. /2012 table 3 . mode register bitmap ba2 ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *2 0 0 pd wr dll tm cas latency bt burst length mode register a8 dll reset a7 mode a3 burst type a2 a1 a0 bl 0 no 0 normal 0 sequential 0 1 0 4 1 yes 1 test 1 interleave 0 1 1 8 note 1: .for ddr2 - 800, wr min is determined by t ck (avg) max and wr max is determined by t ck (avg) min. wr [cycles] = ru {t wr [ns]/t ck (avg)[ns]}, where ru stands f or round up. the mode register must be programmed to this value.this is also used with t rp to determine t dal . note 2: ba2 is reserved for future use and must be set to 0 when programming the mr. ? extende d mod e registe r se t (emr s ) - emr( 1) the extended mode r egister(1) stores the data for enabling or disabling the dll, output driver strength, odt value selection and additive latency. the default value of the extended mode register is not defined, therefore the extended mode register must be w r itten after power - up for proper opera t ion. the extended mode register is written by asserting low on cs#, ras#, cas#, we#, ba1 and high on ba0, while controlling the states of address pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (t m rd ) must be sa ti s f ied t o complete the write operation to the extended mode reg i ster. mode register contents can be changed using the same command and clock cycle requi rements during normal operation as long as all banks are in the precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength data - output driver. a3~a5 determine the additive latency, a2 and a6 are used for odt value se lection, a7~a9 are used for ocd control, a10 is used for dqs# disable. - dl l enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disab led. the dll is automatically disabled when entering self refresh operation and is automatically re - enabled upon exit of se l f refres h operation . an y tim e the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized w i th the external clock. failing to wait for synchronization t o occu r ma y resul t i n a violatio n o f th e t a c o r t dqsck parameters. a12 active power down exit time write recovery for autoprecharge *1 0 fast exit (use t xard ) a11 a10 a9 wr(cycles) a6 a5 a4 cas latency 1 slow exit (use t xards ) 0 0 0 reserved 0 0 0 reserved 0 0 1 2 0 0 1 reserved ba1 ba0 mrs mode 0 1 0 3 0 1 0 reserved 0 0 mr 0 1 1 4 0 1 1 3 0 1 emr(1) 1 0 0 5 1 0 0 4 1 0 emr(2) 1 0 1 6 1 0 1 5 1 1 emr(3) 1 1 0 reserved 1 1 0 6 1 1 1 reserved 1 1 1 reserved
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 11 rev. 1.1 april. /2012 table 4 . extended mode register emr (1) bitmap ba2 ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 *3 0 1 qoff 0 *3 dqs# ocd program rtt additive latency rtt d.i.c dll extended mode register ba1 ba0 mrs mode a6 a2 rtt (nominal) 0 0 mr 0 0 odt disable a0 dl l enable 0 1 emr(1) 0 1 75 0 enable 1 0 emr(2) 1 0 150 1 disable 1 1 emr(3) 1 1 50 a9 a8 a7 ocd calibration program a1 output driver impedance control 0 0 0 ocd calibration mode exit; maintain setting 0 0 1 reserved 0 full strength 0 1 0 reserved 1 r educed strength 1 0 0 reserved 1 1 1 ocd calibration default *1 a5 a4 a3 additive latency 0 0 0 0 a12 qoff *2 0 0 1 1 0 output buffer enabled 0 1 0 2 a10 dqs# 1 output buffer disabled 0 1 1 3 0 enable 1 0 0 4 1 disable 1 0 1 5 1 1 0 reserved 1 1 1 reserved note 1: after setting to default, ocd calibration mode needs to be exited by setting a9 - a7 to 000. note 2: output disabled C dqs, dqss, dqss#.this feature is intended to be used duri ng i dd characterization of read current. note 3: a11 and ba2 are reserved for future use and must be set to 0 when programming the mr.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 11 rev. 1.1 april. /2012 emr(2) the extended mode register (2) controls refresh rela te d features . th e defaul t value of the extended mode registe r (2) is not defined, there f ore the extended mode register (2) must be written after power - up for proper operation. the extended mode register(2) is written by asserting low on cs# , ras# , cas# , we# , hig h on ba1 and low on ba0, while controlling the states of address pins a0 ~ a12. the ddr2 sdram should be in all bank precharge with cke already high prior to w r iting into the extended mode register (2). the mode register set command cycle time ( t m rd ) must be satisfied to complete t he write operation to the ex tended mode register (2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. tabl e 5 . extende d mod e re gister emr(2) bitmap not e 1 : t h e res t bit s i n emrs(2 ) ar e reserve d fo r futur e u s e an d al l bit s i n emrs(2 ) excep t a7 , ba 0 an d ba 1 mus t be programme d t o 0 w he n settin g th e extende d m od e register(2 ) durin g initialization. note 2: du e t o th e migratio n nature , use r need s t o ensur e th e dr am par t su pport s highe r tha n 85 t c as e temperature self - refres h entr y . i f th e hig h temperatu re self - refres h mod e i s suppo r te d the n controlle r ca n se t th e emrs2[a7 ] bi t to enabl e th e self - refres h rat e i n cas e o f highe r tha n 8 5 temperatur e self - refres h operation. not e 3 : ba 2 i s reserve d fo r futur e us e an d m u s t b e se t t o 0 w he n programmin g th e mr.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 12 rev. 1.1 april. /2012 ba2 ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 *1 1 1 0 *1 - emr(3) no function is defined in extended mode register(3).the default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during i nitialization for proper operation. tabl e 6 . extende d mod e registe r em r (3 ) bitmap addre ss field extende d mod e register(3) not e 1 : al l bit s i n em r (3 ) excep t ba 0 an d ba 1 ar e reserve d fo r futur e us e an d mus t b e se t t o 0 w he n progr ammin g th e em r (3).
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 13 rev. 1.1 april. /2012 ? odt (on die termination) on die termination (odt) is a feature that allows a dram to turn on/off termination resistance for each dq, udqs/udqs#, ldqs/ldqs#, udm, and ldm signal via the o d t control pin. the odt feature is designed to i mprov e signa l integrit y o f th e m emory channel by allowing the dram c ontrolle r t o independentl y tur n on/off termination resistance for any or all dram devices. the odt function is supported for active and stan db y modes . i t i s turne d of f an d no t supporte d i n self refres h mode. s w itch (sw 1 , s w 2, s w 3) is enabled by odt p i n. selection among sw 1 , s w 2, and sw3 is determin e d by rtt (nominal) in emr. termination inclu d ed on all dqs, d m, dqs, and dqs# pins tabl e 7 . od t d c electrica l characteristics parameter /condition symbol min. nom. max. unit note rtt effective impedance value for emrs(a6,a2)=0,1; 75 rtt1(eff) 60 75 90 1 rtt effective impedance value for emrs(a6,a2)=1,0;150 rtt2(eff) 120 150 180 1 rtt effective impedance value for emrs(a6,a2)=1,1;50 rtt3(eff) 40 50 60 1 rtt mismatch tolerance between any pull - up/pull - down pair rtt(mis) - 6 - 6 % 2 note 1: measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin seperately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. note 2: measurement defintion for rtt (mis): measure volta ge (vm) at test pin (midpoint) with no load. ( ) ( ) ? 1 100% ?? ?? ?? ??
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 14 rev. 1.1 april. /2012 ? ban k activat e command the bank activate command is issued by holding cas# and we# high with cs# and ras# low at the rising edge of the clock. the bank addresses ba0 - ba2 are used to select the desired bank. the row addresses a0 through a12 are used to determine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be execu ted . immediatel y afte r th e ban k activ e command , the ddr2 sdram can a ccept a read or write command (with or without auto - precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd mi n specification , the n additiv e latenc y must be programmed into the device to delay the r/w co mmand w h ich is internally issued to the device. the additive latency value must be chosen to assure t rcd min is satisfied. additive latencies of 0, 1, 2, 3, and 4 are supported. once a bank has been activated it must be precharged before another bank activa te command can be applied to the same bank. the bank active and precharge times are defined as t ras and t r p , respectively . th e minimu m time interval between successive bank activate commands to the same bank is determined ( t rc ) . th e minimu m time interva l b etwee n ban k activ e command s i s t rrd in order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. there are two rules. one fo r restricting the number of sequential act commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are as follows: - 8 bank device sequential bank activation restriction : no more than 4 banks m ay be activated in a rolling t faw window. converting to clocks is done by dividing t fa w [n s] b y t c k [ns] or t c k [ns], depending on the speed bin, and rounding up to next integer value. as an example of the rolling window, if ru{ ( t faw / t c k ) } or ru{ ( t faw / t c k )} is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued at or between clock n+1 and n+9. - 8 bank device precharge all allowance : t rp for a precharge all command for an 8 bank device will equal to t rp + 1 x t ck or t rp + 1 x t c k , depending on the speed bin, where t rp = ru{ t rp / t c k } and t rp i s t he v a l ue f or a s i n g l e bank precharge. ? rea d an d writ e acces s modes after a bank has been activated, a read or write cycle can be executed. this is ac complished by setting ras# high, cs# and cas# low at the clock s rising edge. we# must also be defined at this time to determine whether the access cycle is a read operation (we# high) or a write operation (w e # low). the ddr2 sdram provides a fast column a ccess operation. a single read or write command will initiate a serial read or write operation on successive clock cycles. the boundary of the burst cycle is str i ctly restricted to specific segments of the page length. any system or application incorporati ng r andom access memory products should be properly designed, tested, and qualified to ensure proper use or access of such memory products. disproportionate, excessive, and/or repeated access to a particular address or add r esses may result in reduction of product life. ? poste d cas# posted cas# operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a cas# read or write command to be issued immediately after the ras ban k activate command (or any tim e durin g th e ras # - cas# - dela y time , t rcd , period) . the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas late n c y (cl). therefore if a user chooses to issue a r/w command before the t rcd min, then al (greater than 0) must be written into the emr(1). the write latency (wl) is always defined as rl - 1 (read latency - 1) where read latency is defined as the sum of addi tive latency plus cas latency (rl=al+cl). read or write operations using al allow seamless bursts (refer to seamless operation timing diagram examples in read burst and write burst section) ? burst mode operation burst mode operation is used to provide a con stant flow of data to memory loc a tions (write cycle), or from memory locations (read cycle). the paramete r s that define how the burst mode w ill operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst m odes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a0 ~ a2 of the mrs. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mrs. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interrup tion of a read or write burst when burst length = 8 is used, see the burst interruption sectio n o f thi s datasheet . a burs t stop command is not supported on ddr2 sdram devices.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 15 rev. 1.1 april. /2012 tabl e 8 . burs t definition , addressin g sequ e nc e o f sequentia l an d interleav e mo de burst length start address sequential interleave a2 a1 a0 4 x 0 0 0 , 1 , 2 , 3 0 , 1 , 2 , 3 x 0 1 1 , 2 , 3 , 0 1 , 0 , 3 , 2 x 1 0 2 , 3 , 0 , 1 2 , 3 , 0 , 1 x 1 1 3 , 0 , 1 , 2 3 , 2 , 1 , 0 8 0 0 0 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 0 0 1 1 , 2 , 3 , 0 , 5 , 6 , 7 , 4 1 , 0 , 3 , 2 , 5 , 4 , 7 , 6 0 1 0 2 , 3 , 0 , 1 , 6 , 7 , 4 , 5 2 , 3 , 0 , 1 , 6 , 7 , 4 , 5 0 1 1 3 , 0 , 1 , 2 , 7 , 4 , 5 , 6 3 , 2 , 1 , 0 , 7 , 6 , 5 , 4 1 0 0 4 , 5 , 6 , 7 , 0 , 1 , 2 , 3 4 , 5 , 6 , 7 , 0 , 1 , 2 , 3 1 0 1 5 , 6 , 7 , 4 , 1 , 2 , 3 , 0 5 , 4 , 7 , 6 , 1 , 0 , 3 , 2 1 1 0 6 , 7 , 4 , 5 , 2 , 3 , 0 , 1 6 , 7 , 4 , 5 , 2 , 3 , 0 , 1 1 1 1 7 , 4 , 5 , 6 , 3 , 0 , 1 , 2 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 ? burs t rea d command the burst read command is initiated by having cs# and cas# low while holding ras# and we# high at the rising edge of th e clock. the address inputs determine the starting col u mn address for the burst. the delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data st r obe output (dqs ) is driven low 1 cl o ck cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data - out appears on the dq pin in phase with the dqs signal in a sou rce synchronous manner. the rl is equal to an additive latency (al) p l us cas latency (cl). the cl is defined by the mode register set (mrs), similar to the existing sdr and ddr sdrams. the a l i s define d b y th e extende d mode register set (1) (emrs (1)). ddr 2 sdram pin timings are specified for either single ended mode or differential mode depending on the settin g o f th e emr s enabl e dqs mod e bit ; timin g advant ages of differential mode are realized in system design. the method by which t he ddr2 sdram pin tim ings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relativ e t o th e crosspoin t o f dq s an d it s complement, dqs#. this distinction in timing methods is guaran t eed by design and characterization. note that when differential data strobe mode is disabled via the emrs, t h e complementar y pin , dqs# , mus t b e tie d externally t o v s s through a 20 ? t o 1 0 k ? resistor to insure proper operation. ? burst w rite operation the burst write command is initiated by having cs#, cas# and we# low while holding ras# high at the rising edge of the clock. the address inputs determine the starting column address. write late ncy (wl) is defined by a read latency (rl) minus one and is equal to (al + cl - 1);and is the nu m ber of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe signa l (dqs) should be driven low (preamble) one clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqs s specification must be satisfied for each positi v e dqs transition to its associated clock edge during wri t e c y cles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when the burst has fini s hed, any additional data suppli ed to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is the write recovery time (wr). ddr2 sdram pin timings are specified for either sing le ended mode or differential mode depending on th e settin g o f th e emr s enabl e dqs mod e bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single en ded mode, timing relationships are measured r e lative to the rising or falling edges of dqs crossing a t th e specifie d ac/d c levels . i n differentia l mode , these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs#. thi s d i stinction in timing methods is guaranteed by design and characterization. note that when differential data s t robe mode is disabled via the emrs, the complementary pin , dqs# , mus t b e tie d externall y t o v s s through a 20 ? t o 10k ? resistor to insure proper operation.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 16 rev. 1.1 april. /2012 ? write data mask one write data mask (dm) pin for each 8 data bits ( d q) will be supported on ddr2 sdrams, consistent with the implementation on ddr sdrams. it has identical timings on write operations as the data bits, and though used in a uni - d irectional manner, is internally loaded identi c ally to data bits to insure matched system timing. dm is not used during read cycles. ? precharg e operation the precharge command is used to precharge or clo s e a bank that has been activated. the precharge comm and is triggered when cs#, ras# and we# are low and cas# is high at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba2, ba1, and ba0 are used to defi ne which bank to precharge when the command is issued. tabl e 9 . ban k selectio n fo r precharg e b y addres s bits a10 ba2 ba1 ba0 precharged bank(s) low low low low ban k 0 only low low low high bank 1 only low low high low bank 2 only low low high high ba nk 3 only low high low low bank 4 only low high low high bank 5 only low high high low bank 6 only low high high high bank 7 only high dont care dont care dont care all banks ? burs t rea d operatio n follo w e d b y precharge minimum read to precharge co mmand spacing to the same bank = al + bl/2 + max (rtp, 2) - 2 clocks. for the earliest possible precharge, the precharge com m and may be issued on the rising edge which additive latency (al) + bl/2 clocks after a read command. a new bank active (command) may be issued to the same bank after the ras# precharge time (t r p ). a precharge command cannot be issued until t ras i s sa ti s fied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4 - bit prefetch of a read to precharge command. this time is called t r t p (read to precharge). for bl = 4 this is the time from the actual read (al after the read command) to precharge command . fo r b l = 8 thi s i s th e tim e fro m a l + 2 clocks after the re ad to the precharge command. ? burst write operation follo w e d by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t w r . for write cycles, a delay must be satisfied from the completion of the last bu r st write cycle until the precharge command can be issued. this delay is known as a write recovery time ( t w r ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t w r delay, as ddr2 sdram does not support an y burst interrupt by a precharge command. t w r is an analog timing parameter and is not the programmed value for t w r i n th e mrs.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 17 rev. 1.1 april. /2012 ? aut o precharg e operation before a new row in an active bank can be opened, t he active bank must be precharged using either the precharge command or the auto - precharge function. when a read or a write command is given to the ddr2 sdram, the cas# timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible m oment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or w rite command is issued, then the auto - precharge function is engaged. during auto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is cas latency (cl) clock cycles befo re the end of the read burst. auto - precharge also be implemented during write commands. the precharge operation engaged by t he auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. thi s feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for r andom data access. the ras# lockout circuit internally delays the precharge operation until the array restore operation has been completed ( t ras satisfied) so that the auto precharge command may be issued with any read or write command. ? burst read w ith auto precharge if a10 is high when a read command is issued, the read with auto - prechar ge function is engaged. the ddr2 sdram starts an auto - precharge operation on the rising edge which is ( a l + bl/2) cycles later from the read with ap command if t ra s (min) and t r t p ar e satisfied . i f t ra s (min) is not satisfied at th e edge , th e star t point of auto - precharge operation will be delayed until t ra s (min) is satisfied. if t r t p (min) is not satisfied at the edge, th e star t poin t o f auto - pre c harge operation will be delayed until t r t p (min) is satisfied. in case the internal precharge is pushed out by t r t p , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto - precharge to the next activate command becomes al + t r t p + t r p . for bl = 8 the time from read with auto - precharge to the next activate command is al + 2 + t r t p + t r p . note that both parameters t r t p and t rp hav e t o b e rounde d u p t o th e nex t intege r value . i n an y event internal precharge does not start earlier than two clocks a ft er t he last 4 - b it pre f e t ch. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras# precharge time (t r p ) has been satisfied from the clock at which the auto - precharge begins. (2) the ras# c y cle time ( t rc ) from the previous bank activation has been satisfied. ? burst w rite w ith auto precharge if a10 is high when a write command is issued, the write with auto - precharge function is engaged. the ddr2 sdram automatically begins precharge operation aft e r the c ompletion of the burst write plus write reco v ery time ( t w r ). the bank undergoing auto - precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) the data - in to bank activate delay time (wr + t r p ) has been satisfied. (2) the ras# c y cle time ( t rc ) from the previous bank activation has been satisfied.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 18 rev. 1.1 april. /2012 fro m command t o command minimu m de la y be t w ee n from command to to command unit note read precharge (to same bank as read) al+bl/2+max(rtp,2) - 2 t 1,2 precharge all al+bl/2+max(rtp,2) - 2 read w/ap precharge (to same bank as read w/ap) al+bl/2+max(rtp,2) - 2 t 1,2 precharge all al+bl/2+max(rtp,2) - 2 write precharge (to same bank as write) wl+bl/2+ t wr t 2 precharge all wl+bl/2+ t wr writ e w /ap precharge (to same bank as write w/ap) wl+bl/2+ t wr t 2 precharge all wl+bl/2+ t wr precharge precharge (to same bank as precharge) 1 t 2 precharge all 1 precharge all precharge 1 t 2 precharge all 1 note 1: rtp [c y cles] =ru {t r t p [ n s ]/t ck (avg) [ns]}, where ru stands for round up. not e 2 : for a given bank, the precharge period should be c ounted from the latest precharge command, either one bank precharge or precharge all, issued to that bank.the prechrage period is satisfied after t rp o r t r p all(= t rp for 8 bank device + 1x t c k ) depending on the latest precharge command issued to that bank. tabl e 10 . precharg e & aut o precharge clariification ck ck ck ck ck ck ? refres h command when cs#, ras# and cas# are held low and we# high at the rising edge of the clock, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the precharge time ( t r p ) before the refresh command (ref) can be applied. an address counter, internal to the device , supplies the bank address during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of t he ddr2 sdram will be in the precharged (idle) state. a delay between the refresh command (ref) and the ne x t activate command or subsequent refresh command must be greater than or equal to the refresh cycle time ( t rfc ).to allow for improved efficiency in scheduling and switching between tasks, some flexibility i n th e absolu t e refres h interva l i s provided . a maximu m o f eight refresh commands can be posted to any given ddr2 s dram , meanin g tha t th e maximu m absolut e interval between any refresh command and the next refresh command is 9 * t ref i . ? self refresh operation the self re fresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built - in timer to accommodate self refresh operation. the self refresh command i s define d b y havin g cs# , ras# , cas # an d cke # hel d l ow with we# high at the rising edge of the clock. odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs comma nd. once the command is registered, cke must be held low to keep the device in self refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refr esh mod e al l o f th e externa l signals except cke, are dont care. for proper self refre s h operation all power supply pins (v dd , v ddq , v ddl and v ref ) must be at valid levels. the dram initiates a minimum of one refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during s e lf refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t ck e . the user may change the external clock frequency or halt the ext ernal clock one clock after self r e fresh entry is registered, however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self refresh e x it is registered, a delay of at least t xsn r must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period t xsr d for proper operation except for self refresh re - entry. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after waiting at least t xsnr period and issuing one refresh command(refresh period of t rfc ). nop or deselect commands must be registered on each positive clock edge during th e sel f refres h exi t interva l t xsn r . odt should be turned off during t xsr d . the use of self refresh mode introduces the possi bilit y tha t a n internall y time d refres h even t can be missed when cke is raised for exit from self ref r esh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh com m and before it is put back into self refresh mode.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 19 rev. 1.1 april. /2012 ? po w e r - do wn power - down is synchronously entere d w hen cke is registered low along with nop or deselect command. no read or write operation may be in progress when cke goes low. these operations are any of the following: read burst or write burst and recovery. cke is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, mode regis t er or extended mode register command time, or autorefresh is in progress. the dll should be in a locked state when power - down is entered. otherwise dll should be reset after exiting power - down mode for proper read operation. if power - down occurs when all banks are precharged, this mode is referred to as precharge power - down; if power - down occurs when there is a row active in any ban k , this mode is referred to as active power - down. fo r active power - down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to low this mode is referred as standard active power - down mode and a fast power - down exi t timin g define d b y th e t xar d timing parameter can be used. when a12 is set to high this mode is referred as a power saving low power active power - down mode. this mode takes longer to exit from the power - down mode and the t xards timing parameter has to be satisfied. entering power - down d eactivates the input and outpu t buffers , excludin g ck , ck# , od t an d cke . als o the dll is disabled upon entering precharge power - down or slow exit active power - down, but the dll is kept enabled during fast exit active power - down. in power - down mode, cke l ow and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are dont care. p o wer - down duration is limited by 9 times t refi o f th e device. the power - down state is synchronously exited when cke is registere d high (along with a nop or deselect command). a valid, executable command can be ap p lied with power - down exit latency, t xp , t xar d or t xard s , after cke goes high. power - down exit latencies are def i ne d i n th e a c spe c tabl e o f thi s dat a sheet. ? as y nchronou s c k e lo w event dram requires cke to be maintained high for all valid operations as defined i n thi s datasheet . i f cke asynchronously drops low during any valid peration dram is not guaranteed to preserve the contents of array . i f thi s even t o ccu r s, memor y c ontrolle r mu st sa t i sf y dra m timin g specificatio n t d elay efore turning off the clocks. stable clocks must exist at the input of dram before cke is rai s ed high again. dram must be fully re - initialized. dram is ready for normal operation after the initial ization sequence. ? inpu t cloc k frequenc y chang e durin g precharg e po w e r do w n ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and c k e mus t b e a t logi c lo w level . a minimu m o f 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock frequency is allowed to change only within minim u m and maximum operating frequency specified for the particular speed grade. during input clock freq uency change, odt and cke must be held at stable low levels. once input clock frequency is changed, stable new clocks must be provided to dram before precharge power down may be exited and dll must be reset via emrs after precharge power down exit. dependi ng on new clock frequency an additional mrs command may need to be issued to appropriately set the wr, cl etc. during dll re - lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency. ? n o operatio n comm and the no operation command should be used in cases when the ddr2 sdram is in an idle or a wait state. the purpose of the no operation command (nop) is to prevent the ddr2 sdram from registering any unwanted commands between operations. a no operation com mand is registered when cs# is low with ras#, cas#, and we# held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. ? deselec t command the deselec t command performs the same function as a no operation command. deselect command occurs when cs# is brought high at the rising edge of the clock, the ras#, cas#, and we# signals become dont cares.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 20 rev. 1.1 april. /2012 tabl e 11 . absolut e maximu m d c ratings s y mbol parameter r ating unit note v dd voltage on v d d pi n relativ e t o vss - 1. 0 ~ 2.3 v 1,3 v ddq voltage on v dd q pi n relativ e t o vss - 0. 5 ~ 2.3 v 1,3 v ddl voltage on v dd l pi n relativ e t o vss - 0. 5 ~ 2.3 v 1,3 v in , v out voltag e o n an y pi n relativ e t o vss - 0. 5 ~ 2.3 v 1,4 t s t g storage temperature - 55~100 c 1 , 2 note1: stress greater than those listed under absolute maximum ratings may cause permanent damage to the devices. this is a stress rating only and functional opera t ion of the device at these or any other conditio ns above those indicated in the operational sections of this specification is not implied. exposure to absolute maximu m ratin g condition s fo r extende d period s ma y affec t reliability. note2: storage temperature is the case tempe r ature on the center/top side of the dram. note3: when v dd and v ddq and v ddl are less than 500mv, vref may be equal to or less than 300mv. note4: voltag e o n an y inpu t o r i/ o ma y no t excee d voltag e o n v ddq . t able 12 . operating temperature condition symbol parameter rating unit not e t oper operating t emperature commercial 0~9 5 c 1,2 industrial - 40~ 9 5 c 1,2 note1: operating temperature is the case surface temperature on center/top of the dram. note2: at 85 ~ 9 5 t ope r , i t i s require d t o se t 3.9u s tref i i n aut o ref r esh mode or to set 1 for emrs(2) bit a7 in self refresh mode. tabl e 13 . recommende d d c opera t in g condition s (sstl_1.8) s y mbol parameter min. t y p. max. unit note v dd powe r suppl y voltage 1.7 1.8 1.9 v 1 v ddl power sup ply voltage for dll 1.7 1.8 1.9 v 5 v ddq powe r suppl y voltag e fo r i/ o buffer 1 .7 1.8 1.9 v 1,5 v ref inpu t referenc e voltage 0.4 9 x v ddq 0. 5 x v ddq 0.5 1 x v ddq mv 2,3 v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v 4 note1: there is no spe cific device vdd supply voltage requirement for sstl_18 compliance. however under all conditions v ddq must be less than or equal to v dd. note2: the value of v ref may be selected by the user to provide optimum noise margin in the system. typically th e valu e o f v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variation s i n v ddq . note3: peak to peak ac noise on v ref ma y no t excee d +/ - 2 % v ref (d c). note4: v t t of transmitting device must track v ref o f receivin g de vice. note5: v ddq t racks wi t h v dd , v ddl t racks wi t h v dd . ac parameters are measured with v dd , v ddq and v ddl tied together
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 21 rev. 1.1 april. /2012 table 14 . input logic level ( v dd = 1.8v 0.1v , t ope r = - 4 0~95 c) s y mbol parameter - 25 unit min. max. v ih (dc) dc input l ogic high voltage v ref + 0.125 v ddq + 0.3 v v il (dc) dc input low voltage - 0.3 v ref - 0.125 v v ih (ac) ac input high voltage v ref + 0.2 v ddq + v peak v v il (ac) a c inpu t lo w voltage vs s q C v peak v ref C 0.2 v v id (ac) a c differentia l voltage 0.5 v ddq v v ix (ac) ac differential crosspoint voltage 0.5 x v ddq - 0.175 0. 5 x v ddq +0.175 v note1: refer to overshoot/undershoot specification for v pea k value: maximum peak amplitude allowed for overshoot and undershoot. table 15 . ac input test conditions ( v dd = 1.8v 0.1v , t ope r = - 4 0~95 c) s y mbol parameter - 25 unit note v ref inpu t referenc e voltage 0. 5 x v ddq v 1 v s w ing(ma x ) inpu t signa l maximu m pea k t o pea k swing 1 .0 v 1 sle w rate inpu t signa l minimu m sle w rate 1.0 v/ns 2 , 3 note1: input wavefo rm timing is referenced to the input signal crossing through the v ih / il (ac) level applied to the devic e unde r test. note2: the input signal minimum slew rate is to be maintained over the range from v ref t o v ih (ac) min for rising edges and the range from v ref t o v il (ac ) ma x fo r fallin g edge s . note3: ac timings are referenced with input waveforms switching from v il (a c) t o v ih (ac) on the positive transitions and v ih (a c) t o v il (ac) on the negative transitions. table 16 . differential ac output paramete rs ( v dd = 1.8v 0.1v , t ope r = - 4 0~95 c) s y mbol parameter - 25 unit note min. max. v o x (ac) a c differentia l cros s poin t voltage 0.5x v ddq - 0.125 0.5xv ddq +0.125 v 1 note1: th e typica l valu e o f v ox (ac ) i s expecte d t o b e abou t 0. 5 x v ddq of the tr ansmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at which differential output signals must cross. tabl e 18 . a c overshoot/undershoo t specif i catio n fo r addres s an d contro l pins (a0 - a12 , ba0 - ba2 , cs# , r as# , cas# , we# , cke , odt) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0.5 v maximum peak amplitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.66 v - ns maximum undershoot area below v ss 0.66 v - ns
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 22 rev. 1.1 april. /2012 tabl e 18 . a c overshoot/undershoo t specification for clock, data, strobe, and mask pins (dq, udqs, ldqs, udqs#, ldqs#, dm, ck, ck#) parameter - 25 unit maximum peak amplitude allowed for overshoot area 0.5 v maximum peak amplitude allowed for undershoot area 0.5 v maximum overshoot area above v dd 0.23 v - ns maximum undershoot area below v ss 0.23 v - ns table 19 . output ac test conditions ( v dd = 1.8v 0.1v , t ope r = - 4 0~95 c) s y mbol parameter - 25 unit note v o t r outpu t timin g measuremen t referenc e level 0 .5x v ddq v 1 note1: th e v ddq of the device under test is referenced. table 20 . output dc current drive ( v dd = 1.8v 0.1v , t ope r = - 4 0~95 c) s y mbol parameter - 25 unit note i oh (dc) output minimum source dc current - 13.4 ma 1, 3, 4 i o l (dc) output mi nimum sink dc current 13.4 ma 2, 3, 4 note1: v ddq = 1. 7 v ; v out = 1420 mv. ( v out - v ddq ) /i oh must be less than 21 ? fo r value s o f v out between v ddq and v ddq - 28 0 mv. note2: v ddq = 1. 7 v ; v out = 28 0 mv . v ou t /i ol must be less than 21 ? fo r value s o f v out betwee n 0 v an d 28 0 mv. note3: th e d c valu e o f v ref applie d t o th e receivin g devic e i s se t t o v tt note4: th e value s o f i oh (dc) and i ol (dc) are based on the conditions given in notes 1 and 2. they are used to test device drive current capability to ensure v ih min plus a noise margin and vil max minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating point (see jedec standard: section 3.3 of jesd8 - 15a) along a 21 ? loa d lin e t o defin e a convenient driver current for measurement. tabl e 21 . capacitanc e ( v dd = 1.8v, f = 1mhz, t ope r = 25 c) s y mbol parameter - 25 unit min. max. c in input capacitance : command and address 1.0 1.75 pf c ck input capacitance (c k, ck#) 1.0 2.0 pf c i/o dm , dq , dq s input/outpu t capacitance 2.5 3.5 pf note: these parameters are periodically sampled and are not 100% tested.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 2 3 rev. 1.1 april. /2012 tabl e 22 . id d specificatio n p arameters and test conditions ( v dd = 1.8v 0.1v , t ope r = - 4 0~95 c) paramete r & tes t condition s y mbol - 25 unit max. operating one bank acti v e - precharge current: t ck = t ck (min) , t rc = t rc (min) , t ras = t ra s (min) ; ck e i s high , cs # is high between valid commands; address bus inputs are switching; data bus inputs are switch ing i dd0 115 ma operating one bank acti v e - read - precharge current: i out = 0ma ; b l = 4 , c l = c l (min) , a l = 0 ; t ck = t ck (min),t rc = t rc (min), t ras = t ra s (min) , t rcd = t rcd (min);cke is high, cs# is high between valid commands;address bus inputs ar e switching; data pattern is same as i dd4w i dd1 130 ma precharge po w er - do w n current: all banks idle; t ck = t ck (min); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 10 ma precharge quiet standby current: all banks idle; t ck = t ck (min) ; ck e i s high , cs # i s high ; othe r c ontrol and address bus inputs are stable; data bus inputs are floating i dd2q 60 ma precharge standby current: all banks idle; t ck = t ck (min); cke is high, cs# is high; other co ntrol and address bus inputs are switching; data bus inputs are switching i dd2n 65 ma acti v e po w er - do w n current: all banks open; t ck = t ck (min); cke is low; other control and address bus inputs are stable; data bus inputs are floating mrs(a12)=0 i dd3p 30 ma mrs(a12)=1 10 ma acti v e standby current: all banks open; t ck = t c k (min), t ras = t ras (ma x ), t rp = t rp (min); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switc hing i dd3n 75 ma operating burst w rite current: all banks open,continuous burst writes; bl = 4, cl = cl (min), al = 0; t c k = t ck (min), t ras = t ras (ma x ), t rp = t rp (min); cke is high, cs# is high between valid commands; address bus inputs are swit ching; data bus inputs are switching i dd4w 235 ma operating burst read current: all banks open, continuous burst reads, i out = 0m a ; b l = 4, cl = cl (min), al = 0; t ck = t ck (min), t ras = t ras (ma x ), t rp = t rp (min); cke is high, cs# is high betwee n valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 235 ma burst refresh current: t ck = t ck (min); refresh command at every t rfc (min ) interval ; ck e is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 210 ma self refresh current: c k an d ck # a t 0v ; ck e 0.2v;other control and address bus inputs are floating; data bus inputs are floating i dd6 9 ma operating bank inter lea v e read current: all bank interleaving reads, i ou t = 0m a ; b l = 4, cl = cl (min), a l = t rcd (min) - 1 x t ck (min) ; t ck = t ck (min) , t rc = t rc (min) , t rrd = t rrd (min) , t rcd = t rcd (min) ; ck e i s high , cs # i s high between valid commands; address bus inputs a re stable during deselects.data pattern is same as idd4r i dd7 330 ma
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 24 rev. 1.1 april. /2012 table 23. electrical characteristics and recommended a.c. operating conditions (v dd = 1 . 8 v ? 0.1v , t oper = - 40~ 95 ? c) symbol parameter - 25 unit specific notes min. max. t ck(avg) average clock period cl=3 5 8 ns 15, 33, 34 cl=4 3.75 8 ns cl=5 2.5 8 ns cl=6 2.5 8 ns t ch(avg) average clock high pulse width 0.48 0.52 t ck 34, 35 t cl(avg) average clock low pulse width 0.48 0.52 t ck 34, 35 wl write command to dqs associated clock edge rl - 1 t ck t dqss dqs latching rising transitions to associated clock edges - 0.25 0.25 t ck 28 t dss dqs falling edge to ck setup time 0.2 - t ck 28 t dsh dqs falling edge hold time from ck 0.2 - t ck t dqsh dqs input high pulse widt h 0.35 - t ck t dqsl dqs input low pulse width 0.35 - t ck t wpre write preamble 0.35 - t ck t wpst write postamble 0.4 0.6 t ck 10 t is(base) address and control input setup time 0.175 - ns 5, 7, 9, 22, 27 t ih(base) address and control input hold time 0.2 5 - ns 5, 7, 9, 23, 27 t ipw control & address input pulse width for each input 0.6 - t ck t ds(base) dq & dm input setup time 0.05 - ns 6 - 8, 20, 26, 29 t dh(base) dq & dm input hold time 0.125 - ns 6 - 8, 21, 26, 29 t dipw dq and dm input pulse width for e ach input 0.35 - t ck t ac dq output access time from ck, ck# - 0.4 0.4 ns 38 t dqsck dqs output access time from ck, ck# - 0.35 0.35 ns 38 t hz data - out high - impedance time from ck, ck# - t ac (max) ns 18, 38 t lz(dqs) dqs(dqs#) low - impedance time from ck, ck # t ac (min) t ac (max) ns 18, 38 t lz(dq) dq low - impedance time from ck, ck# 2t ac (min) t ac (max) ns 18, 38 t dqsq dqs - dq skew for dqs and associated dq signals - 0.2 ns 13 t hp ck half pulse width min (t ch ,t cl ) - ns 11, 12, 35 t qhs dq hold skew factor - 0.3 n s 12, 36 t qh dq/dqs output hold time from dqs t hp - t qhs - ns 37 t rpre read preamble 0.9 1.1 t ck 19, 39 t rpst read postamble 0.4 0.6 t ck 19, 40 t rrd active to active command period 10 - ns 4, 30 t faw four activate window 45 - ns 4, 30 t ccd cas# to c as# command delay 2 - t ck t wr write recovery time 15 - ns 30 t dal auto power write recovery + precharge time wr + t rp - ns 14, 31 t wtr internal write to read command delay 7.5 - ns 3, 24, 30 t rtp internal read to precharge command delay 7.5 - ns 3, 3 0 t cke cke minimum pulse width 3 - t ck 25
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 25 rev. 1.1 april. /2012 t xsnr exit self refresh to non - read command delay t rfc +10 - ns 30 t xsrd exit self refresh to a read command 200 - t ck t xp exit precharge power down to any command 2 - t ck t xard exit active power down to read command 2 - t ck 1 t xards exit active power down to read command (slow exit, lower power) 8 - al - t ck 1, 2 t aond odt turn - on delay 2 2 t ck 16 t aon odt turn - on t ac (min) t ac (max) +0.7 ns 6, 16, 38 t aonpd odt turn - on (power - down mode) t ac (min) +2 2 t ck +t ac ( max) +1 ns t aofd odt turn - off delay 2.5 2.5 t ck 17, 42 t aof odt turn - off t ac (min) t ac (max) +0.6 ns 17, 41, 42 t aofpd odt turn - off (power - down mode) t ac (min) +2 2.5 t ck +t ac (max) +1 ns t anpd odt to power down entry latency 3 - t ck t axpd odt power down e xit latency 8 - t ck t mrd mode register set command cycle time 2 - t ck t mod mrs command to odt update delay 0 12 ns 30 t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck +t ih - ns 15 t rfc refresh to active/refresh comman d time 127.5 - ns 43 t refi average periodic refesh interval @ - 40 Q tc Q +85 - 7.8 43 @ +85 tc Q +95 - 3.9 43 t rcd ras# to cas# delay time 12.5 - ns t rp row precharge delay time 12.5 - ns t rc row cycle delay time 57.5 - ns t ras row active delay time 45 70k ns
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 26 rev. 1.1 april. /2012 general notes, w h ich may apply for all ac parameters: note 1: ddr2 sdram ac ti mi ng reference load the below figure represents the timing reference load used i n definin g th e relevan t timin g parameter s o f th e part. it is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. the output timing reference voltage level for single ended s i gnals is the crosspoint with vtt . the output timing reference voltage level for differential signals is the cro sspoin t o f th e tru e (e.g . dqs ) an d th e complemen t (e.g. dqs#) signal. not e 2 : sle w rat e measuremen t le v e ls a) output slew rate for falling and rising edges is measured between v t t - 250 mv and v t t + 250 mv for single ended signals. for differential signals (e.g. dqs C dqs#) output slew rate is measured between dqs C dqs# = - 500 mv and dqs C dqs# = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b) input slew rate for single ended signals is measured from v ref (d c) t o v ih (ac), min for rising edges and from v ref (d c) t o v i l (ac),max for falling edges.for differential signals (e.g. ck C ck#) slew rate for rising edges is measured from ck C ck# = - 250 mv to ck - ck# = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) v id is the magnitude of the difference between the i npu t voltag e o n c k an d th e inpu t voltag e o n ck# , or betweendqs and dqs# for differential strobe. note 3: ddr2 sdram output slew rate test load output slew rate is characteri z ed under the test conditions as below
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 27 rev. 1.1 april. /2012 note 4: differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the settin g o f th e emr s enab l e dqs mod e bit ; timin g advant ages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs#. this distinction in timing methods is guaran t eed by design and characterization. note tha t when differential data strobe mode is disabled via the emrs, the complementary pin, dqs#, must be tied externally to v s s through a 20 ? t o 1 0 k ? resistor to insure proper operation note 5: ac timings are for linear signal transitions. note 6 : all voltages are referenced to v ss . note 7 : these parameters guarantee device beha v ior, but they are not necess a rily tested on each device.they may be guaranteed by device design or tester correlation note 8: tes t s f or a c ti ming, i dd , and electrical (ac and dc) characteris t ics, may be conducted at nominal reference/supply voltage levels, but the related spe c ifications and device operation are guaran teed for the full voltage range specified. specifi c note s fo r dedicate d a c parameters note 1 : user can choose which active power down exi t timin g t o us e vi a mr s (bi t 12) . t xar d is expected to be used for fast active power down exit timing. t xards is expec ted to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. note 2: al=additiv e latency. note 3 : this is a minimum requirement. minimum read to precharge timing is al+bl/2 provided that the t r t p an d t ras (min) have been satisfied. note 4: a minimum of t wo clocks (2* t c k ) is required irrespective of operating frequency. note 5: timings are specified with command/add r es s inpu t sle w rat e o f 1. 0 v/ns. note 6 : timings are specified with dqs, dm, and dq ss ( i n single ended mode) input slew rate of 1.0v/ns. note 7 : timings are specified with ck/ck# differential s l ew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in d i fferential strobe mode and a slew rat e of 1 v/ns in single ended mode. note 8 : data setup and hold time derating. for all input signals the total t ds (setup time) and t dh (hold time) required is calculated by adding the data sheet. t ds(base ) and t dh(base ) valu e t o th e ? t ds and ? t dh deratin g valu e respectively. example : t ds (total setup time) = t d s (base ) + ? t d s .for slew rates in between the values listed in tables 28, the derating values may obtained by linear interpolation.the s e values are typically not subject to produ ction test. they are verified by design and characterization. tabl e 24 . ddr2 - 80 0 tds/td h dera ting w ith differential data strobe tds, td h deratin g v a lue s fo r dd2 - 800 ( a l l unit s i n ps ; th e not e applie s t o th e entir e table) dqs,dqs # differentia l sle w rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h td s td h dq slew rate v/ns 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - - 5 - 14 - 5 - 14 7 - 2 19 10 31 22 - - - - - - 0.8 - - - - - 13 - 31 - 1 - 19 11 - 7 23 5 35 17 - - - - 0.7 - - - - - - - 10 - 42 2 - 30 14 - 18 26 - 6 38 6 - - 0.6 - - - - - - - - - 10 - 59 2 - 47 14 - 35 26 - 23 38 - 11 0.5 - - - - - - - - - - - 24 - 89 - 12 - 77 0 - 65 12 - 53 0.4 - - - - - - - - - - - - - 52 - 140 - 40 - 128 - 28 - 116
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 28 rev. 1.1 april. /2012 note 9 : t is and t ih (input setup and hold) derating for all input signals the total t is (setup time) and t ih (hold time) required is calculated by adding the data sheet t is(base ) and t ih(base ) valu e t o th e ? t is and ? tih deratin g valu e respectively . example : t is (total setup time) = t i s (base) + ? t is for slew rates in between the values listed in t able s 29 , th e deratin g value s ma y obtaine d b y linear interpolation.these values are typically not subje c t t o productio n test . the y ar e verifie d b y desig n and characterization tabl e 25 . deratin g value s fo r ddr2 - 800 ti s an d ti h deratin g value s fo r dr2 - 800 ck,ck# differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns tis tih tis tih tis tih units notes command/ a ddress slew rate (v/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 + 163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 - 5 - 14 +25 +16 +55 +46 ps 1 0.8 - 13 - 31 +17 - 1 +47 +29 ps 1 0.7 - 22 - 54 +8 - 24 +38 +6 ps 1 0.6 - 34 - 83 - 4 - 53 +26 - 23 ps 1 0.5 - 60 - 125 - 30 - 95 0 - 65 ps 1 0.4 - 100 - 188 - 70 - 158 - 40 - 128 ps 1 0.3 - 168 - 292 - 138 - 262 - 108 - 232 ps 1 0.25 - 200 - 375 - 170 - 345 - 140 - 315 ps 1 0.2 - 325 - 500 - 295 - 470 - 265 - 440 ps 1 0.15 - 51 7 - 708 - 487 - 678 - 457 - 648 ps 1 0.1 - 1000 - 1125 - 970 - 1095 - 940 - 1065 ps 1 note 10: the maximum limit for this parameter is not a de v ice limit. the device will operate with a greater value for this parameter, but system performan c e (bus turnaround) wi ll degrade accordingly. note 11: min ( t c l , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be g r eater than the minimum specification limits for t c l and t ch ). note 12: t qh = t hp C t qh s , where: t hp = minimum half clock period for any given cyc l e and is defined by clock high or clock low ( t ch , t c l ). t qhs accounts for: 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one transit ion f o llowed by the worst case pull - in of dq on the next transition , bot h o f whic h are , separately , du e t o data pin skew and output pattern effects, and p - channel t o n - channe l variatio n o f th e outpu t drivers. note 13: t dqs q : consists of data pin skew and o utput pattern eff e cts, and p - channel to n - channel variation of the output drivers as well as output s l ew rate mismatch between dqs / dqs# and associated dq in any given c y cle. note 14: t dal = wr + ru{ t r p [n s] / t c k [ns] }, where ru stands for round up.wr r efers to the t w r parameter stored in the mrs. for t r p , if the result of the division is not al read y a n integer , roun d u p t o th e nex t highes t integer. t ck refers to the application clock period. note 15: the clock frequency is allowed to change during self C refresh mode or precharge power - down mode. in case of clock frequency change during precharge power - down. note 16: odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt re sis t ance is fully on. both are measured from t aond , which is interpreted differently per speed bin. for ddr2 - 800/1066, t aond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 29 rev. 1.1 april. /2012 note 17: odt turn off time min is when the device starts to tur n of f od t resistance . od t tur n of f tim e ma x is when the bus is in high impedance. both are measured from t aof d , which is interpreted differently per speed bin. for ddr2 - 667, if t c k (avg) = 3 ns is assumed, t aofd is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edges. note 18: t hz and t l z transitions occur in the same access time as valid data transitio ns. these parameters are referenced to a specific voltage level which spe c ifies when the device output is no longer driving ( t hz ), or begins driving ( t l z ). note 19: t rps t end point and t rpre begin point are not referenced to a spe c ifi c voltag e leve l bu t s pecif y whe n the device output is no longer driving ( t rps t ), or begins driving ( t rpr e ). the actual voltage measurement points are not critical as long as the calculation is consistent. note 20: inpu t wavefor m timin g t ds with differential data strobe enable d mr[bit10]=0, is referenced from the input signal crossing at the v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v i l (ac) level to the differential data strobe crosspoint for a fallin g signal applied to the device under test. dqs, dqs# signals must be monotonic between v i l (dc)max and v ih (dc)min. note 21: inpu t wavefor m timin g t dh with differential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe crosspo int to the input signal crossing at the v ih (dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v i l (dc) level for a rising signal applied to the device under test. dqs, dqs# signals must be mo notonic between v i l (dc)max and v ih (dc)min. note 22: input waveform timing is referenced f r om the input signal crossing at the v ih (ac) level for a rising signal and v i l (ac) for a falling signal applied to the device under test. note 23: input waveform tim ing is referenced f r om the input signal crossing at the v i l (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test. note 24: t w t r is at lease t wo clocks (2 x t ck ) independent of operation frequency. note 25: t ck e min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke mus t remai n a t th e vali d inpu t leve l th e entir e tim e i t takes to achieve the 3 clocks of registration. thus, after an y ck e transition , ck e ma y no t transitio n fro m i t s vali d leve l durin g th e tim e perio d o f t is + 2 x t ck + t ih . note 26: i f t ds or t dh is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed. note 27: these parameters are measured from a command/address signal (cke, cs#, ras#, cas#, we#, odt, ba0, a0, a1, etc.) transition edge to its respective cl o ck signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t ji t (per), t ji t (cc), etc.), as the se tup and hold are relative to the clock signal crossing that latches the command / address. that is, these parameters should be met whether clock jitter is present or not. note 28: these parameters are measured from a data strobe signal (ldqs/udqs) crossing to its respective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t ji t (per), t ji t (cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether c lock jitter is present or not. note 29: these parameters are measured from a data signal ((l/u) dm, (l/u) dq0, (l/u) dq1, etc.) transition edge to its respective data strobe signal (ldqs/udqs/ldqs#/udqs#) crossing. note 30: for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tpara m / t c k (avg)}, which is in clock cycles, assuming all i nput clock jitter specifications are satisfied. note 31: t dal [t c k ] = w r [ t c k ] + tr p [t c k ] = wr + ru { t rp [p s] / t c k (avg) [ps] }, where wr is the value programmed in the mode register set. note 32: new units, t c k (avg) is introduced in ddr2 - 1066 and ddr2 - 800. unit t c k (avg) represents the actual t c k (avg) of the input clock under operation. note 33: input clock jitter spec para meter. these parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these pa r ameters apply to ddr2 - 1066 and ddr2 - 800 only. the jitter specified is a random jitter meeting a gaussian distribution.
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 30 rev . 1.1 april. /2012 table 26 . i nput clock jitter spec parameter parameter s y mbol ddr2 - 800 - 25 units notes min. max. clock period jitter t jit ( per) - 100 100 ps 33 clock period jitter during dll locking period t jit (per,lck) - 80 80 ps 33 c y cle t o c y cle clock period ji tt er t ji t (cc) - 200 200 ps 33 cycle to cycle clock period jitter during dll locking period t jit (cc,lck) - 160 160 ps 33 cumulati v e error across 2 c y cles t err (2per) - 150 150 ps 33 cumulati v e error across 3 c y cles t err (3per) - 175 175 ps 33 cumulati v e error across 4 c y cles t err (4per) - 200 200 ps 33 cumulati v e error across 5 c y cles t err (5per) - 200 200 ps 33 cumulative error across n cycles, n=6...10, inclusive t err (6 - 10per) - 300 300 ps 33 cumulative error across n cycles, n=11...50, inclusive t err (11 - 50per) - 450 450 ps 33 dut y c y c l e jitter t jit (duty) - 100 100 ps 33 note 34: these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolu t e inst antaneous timing holds at all times. (min andma x o f spe c value s ar e t o b e use d f o r calculations in the table below.) tabl e 27 . absolut e cloc k perio d averag e values parameter s y mbol min. max. unit a bsolu t e clock period t ck (abs) t c k (a v g),min + t ji t (per) ,min t c k (a v g),max + t ji t (per),max ps a bsolu t e clock h i gh pulse wid t h t ch (abs) t ch (a v g),min * t c k (a v g),min + t ji t (duty),min t ch (a v g),max * t c k (a v g),max + t ji t (duty),max ps absolute clock low pulse width t cl (abs) t c l (a v g),min * t c k (a v g),min + t ji t (duty), min t c l (a v g), max * t c k (a v g),max + t ji t ( duty ), max ps note 35: t hp i s th e minimu m o f th e absolut e hal f period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs t o deriv e th e dra m outpu t timin g t qh . the value to be used for tqh calculation is determined by the following equation; t hp = min ( t ch (abs), t c l (abs) ), where, t ch (abs) is the minimum of the actual instantaneous clock high time; t c l (abs) is the minimum of the a c tual instantaneous clock low time; note 36: t qhs accounts for: 1) the pulse duration distortion of on - chip clock circuits, which represents how well the actual t hp a t th e input is transferred to the output; and 2) the worst case push - out of dqs on one transition f o llowed by the worst case pull - in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p - channel to n - channel variation of the output drivers
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 31 rev . 1.1 april. /2012 note 37: t qh = t hp C t qh s , where : t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the l e ss half - pulse width distortion present, the larger the t qh valu e is ; an d th e large r th e vali d dat a ey e wil l be.} note 38: wh en the device is operated with input clock jitter, this parameter needs to be derated by the actual t err (6 - 10per) of the input clock. ( output deratings are relative to the sdram input clock.) note 39: when the device is operated with input clock jitter, t his parameter needs to be derated by the actual tjit(per) of the input clock. (output derat i ngs are relative to the sdram input clock.) note 40: when the device is operated with input clock jitter, this parameter needs to be derated by the actual t ji t (dut y ) o f th e inpu t clock . (outpu t derating s are relative to the sdram input clock.) note 41: when the device is operated with input clock jitter, this parameter needs to be derated by { - t ji t (duty),max - t err (6 - 10per),max } and { - t ji t (duty),min - t err (6 - 1 0per),min } of the actual input clock. (output deratings are relative to the sdram input clock.) note 42: for t aofd of ddr2 - 800/1066, t he 1/2 clock of t ck in the 2.5 x t ck assumes a t ch (avg), average input clock high pulse width of 0.5 relative to t c k (a v g ). t ao f ,min and t ao f ,max should each be derated by the same amoun t a s th e actua l amoun t o f t ch (avg ) offse t presen t a t th e dra m inpu t wit h respec t t o 0.5. note 43: if refresh timing is violated, data corruption may occur and the data must be re - writtern wi th valid data before a valid read can be executed timing waveforms figure 7. initialization sequence after power - up
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 32 rev . 1.1 april. /2012 figure 8. odt update delay timing - tmod figure 9. odt update delay timing - t mod , as measured from outside c k c k # t c h c k e c o m m a n d t c l t i s o d t t i s n o p p r e a l l e m r s m r s p r e a l l r e f r e f m r s e m r s e m r s a n y c m d 4 0 0 n s t r p t m r d t m r d t r p t m r d f o l l o w o c d f l o w c h a r t t o i t m i n 2 0 0 c y c l e d l l e n a b l e d l l r e s e t o c d d e f a u l t o c d c a l . m o d e e x i t n o t e 1 : t o g u a r a n t e e o d t o f f , v r e f m u s t b e v a l i d a n d a l o w l e v e l m u s t b e a p p l i e d t o t h e o d t p i n . t r f c t r f c c k u p d a t i n g r t t t i s e m r s n o p n o p n o p n o p n o p c m d t a o f d t m o d , m a x t m o d , m i n o l d s e t t i n g n e w s e t t i n g o d t n o t e 1 : t o p r e v e n t a n y i m p e d a n c e g l i t c h o n t h e c h a n n e l , t h e f o l l o w i n g c o n d i t i o n s m u s t b e m e t : - t a o f d m u s t b e m e t b e f o r e i s s u i n g t h e e m r s c o m m a n d . - o d t m u s t r e m a i n l o w f o r t h e e n t i r e d u r a t i o n o f t m o d w i n d o w , u n t i l t m o d , m a x i s m e t . t h e n t h e o d t i s r e a d y f o r n o r m a l o p e r a t i o n w i t h t h e n e w s e t t i n g , a n d t h e o d t s i g n a l m a y b e r a i s e d a g a i n t o t u r n e d o n t h e o d t . n o t e 2 : e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . n o t e 3 : " s e t t i n g " i n t h i s d i a g r a m i s t h e r e g i s t e r a n d i / o s e t t i n g , n o t w h a t i s m e a s u r e d f r o m o u t s i d e . c k #
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 33 rev . 1.1 april. /2012 figure 10. odt timing for active standby mode figure 11. odt timing for power - down mode c k # c k r t t t i s e m r s c m d t a o f d t m o d , m a x o l d s e t t i n g n e w s e t t i n g o d t n o p n o p n o p n o p n o p t a o n d n o t e 1 : e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . n o t e 2 : " s e t t i n g " i n t h i s d i a g r a m i s m e a s u r e d f r o m o u t s i d e . c k # t 0 i n t e r n a l t e r m r e s . t i s t i s t a o n d c k t 1 t 2 t 3 t 4 t 5 t 6 c k e o d t v i h ( a c ) t i s v i l ( a c ) t a o f d t a o n , m i n t a o n , m a x t a o f , m i n t a o f , m a x r t t
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 34 rev . 1.1 april. /2012 figure 12. odt timing mode switch at entering power - down mode figure 13.odt timing mode switch at exit power - down mode c k # t 0 i n t e r n a l t e r m r e s . t i s c k t 1 t 2 t 3 t 4 t 5 t 6 c k e o d t v i h ( a c ) t i s v i l ( a c ) t a o f p d , m a x t a o n p d , m i n r t t t a o f p d , m i n t a o n p d , m a x c k # c k t i s c k e t a o f d t a o n d o d t t a n p d t - 5 t - 4 t - 3 t - 2 t - 1 t 0 t 1 t 2 t 3 t 4 e n t e r i n g s l o w e x i t a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e . r t t i n t e r n a l t e r m r e s . t i s v i l ( a c ) o d t r t t i n t e r n a l t e r m r e s . t i s v i l ( a c ) t a o f p d m a x a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . t i s v i h ( a c ) r t t a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . t a o n p d m a x t i s v i h ( a c ) p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . r t t o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s .
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 35 rev . 1.1 april. /2012 figure 14. bank activate command cycle (t rcd =3, al=2, t rp =3, t rrd =2, t ccd =2) figure 15. posted cas# operation: al=2 read followed by a write to the same bank c k # c k t i s c k e t a o f d t a o n d o d t t a x p d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 e x i t i n g f r o m s l o w a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e . i n t e r n a l t e r m r e s . t i s v i l ( a c ) o d t i n t e r n a l t e r m r e s . t i s v i l ( a c ) a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . t i s v i h ( a c ) a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d . t a o n p d m a x t i s v i h ( a c ) p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d . o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . r t t t a o f p d m a x v i h ( a c ) r t t r t t r t t c k # t 0 t 1 t 2 t 3 t n t n + 1 t n + 2 i n t e r n a l r a s # - c a s # d e l a y ( > = t r c d m i n ) c a s # - c a s # d e l a y t i m e ( t c c d ) t r c d = 1 r e a d b e g i n s t n + 3 b a n k a r o w a d d r . b a n k a c o l . a d d r . b a n k b r o w a d d r . b a n k b c o l . a d d r b a n k a a d d r . b a n k b a d d r . b a n k a r o w a d d r . a d d i t i v e l a t e n c y d e l a y ( a l ) b a n k a a c t i v a t e b a n k a p o s t c a s # r e a d b a n k b a c t i v a t e b a n k b p o s t c a s # r e a d b a n k a p r e c h a r g e b a n k b p r e c h a r g e b a n k a a c t i v a t e r a s # - r a s # d e l a y t i m e ( > = t r r d ) b a n k a c t i v e ( > = t r a s ) b a n k p r e c h a r g e t i m e ( > = t r p ) r a s # c y c l e t i m e ( > = t r c ) a d d r e s s c o m m a n d c k
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 36 rev . 1.1 april. /2012 figure 16. posted cas# operation: al=0 read followed by a write to the s ame bank figure 17. data output (read) timing c k # c m d a l = 2 - 1 1 2 3 4 5 6 7 8 9 0 1 0 1 1 1 2 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k c l = 3 w l = r l - 1 = 4 d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 r l = a l + c l = 5 > = t r c d [ a l = 2 a n d c l = 3 , r l = ( a l + c l ) = 5 , w l = ( r l - 1 ) = 4 , b l = 4 ] d q s d q c k d q s # c k # c m d a l = 0 - 1 1 2 3 4 5 6 7 8 9 0 1 0 1 1 1 2 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k c l = 3 w l = r l - 1 = 2 d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 r l = a l + c l = 3 > = t r c d [ a l = 0 a n d c l = 3 , r l = ( a l + c l ) = 3 , w l = ( r l - 1 ) = 2 , b l = 4 ] d q s d q c k d q s #
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 37 rev . 1.1 april. /2012 figure 18. burst read operation: rl=5 (al=2, cl=3, bl=4) figure 19. burst read operation: rl=3 (al =0, cl=3, bl=8) figure 20. burst read followed by burst write: rl=5, wl= (rl - 1) =4, bl=4 c k # c k d q t d q s q m a x c k t c h t r p s t t r p r e d q s t c l d q s # d q s q q q t q h q t q h t d q s q m a x d q s # c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 p o s t e d c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p n o p = < t d q s c k d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 a l = 2 c l = 3 r l = 5 d q s # c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 r e a d a n o p n o p n o p n o p n o p n o p n o p n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 c l = 3 r l = 3 d q s # = < t d q s c k d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 38 rev . 1.1 april. /2012 figure 21. seamless burst read operation: rl=5, al=2, cl=3, bl=4 figure 22. read burst interrupt timing: (cl=3, al=0, rl=3, bl=8) c k c k # d q s c m d d q s t 0 t 1 t n - 1 t n t n + 1 t n + 2 t n + 3 t n + 4 t n + 5 p o s t c a s # r e a d a n o p n o p p o s t c a s # w r i t e a n o p n o p n o p n o p n o p d o u t a 0 r l = 5 d q s # t r t w ( r e a d t o w r i t e t u r n a r o u n d t i m e ) w l = r l - 1 = 4 d o u t a 1 d o u t a 2 d o u t a 3 d i n a 0 d i n a 1 d i n a 2 d i n a 3 n o t e : t h e m i n i m u m t i m e f r o m t h e b u r s t r e a d c o m m a n d t o t h e b u r s t w r i t e c o m m a n d i s d e f i n e d b y a r e a d - t o - w r i t e - t u r n - a r o u n d - t i m e , w h i c h i s 4 c l o c k s i n c a s e o f b l = 4 o p e r a t i o n , 6 c l o c k s i n c a s e o f b l = 8 o p e r a t i o n . c k c k # d q s c m d d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 p o s t c a s # r e a d a n o p p o s t c a s # r e a d b n o p n o p n o p n o p n o p n o p d o u t a 0 a l = 2 d q s # d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 c l = 3 r l = 5 n o t e : t h e s e a m l e s s b u r s t r e a d o p e r a t i o n i s s u p p o r t e d b y e n a b l i n g a r e a d c o m m a n d a t e v e r y o t h e r c l o c k f o r b l = 4 o p e r a t i o n , a n d e v e r y 4 c l o c k f o r b l = 8 o p e r a t i o n . t h i s o p e r a t i o n i s a l l o w e d r e g a r d l e s s o f s a m e o r d i f f e r e n t b a n k s a s l o n g a s t h e b a n k s a r e a c t i v a t e d .
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 39 rev . 1.1 april. /2012 figure 23. data input (write) timing figure 24. burst write operation: rl=5 (al=2, cl=3), wl=4, bl=4 c k # c k c m d r e a d a n o p r e a d b n o p n o p n o p n o p n o p n o p n o p a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d q s d q s # d q s n o t e 1 : r e a d b u r s t i n t e r r u p t f u n c t i o n i s o n l y a l l o w e d o n b u r s t o f 8 . b u r s t i n t e r r u p t o f 4 i s p r o h i b i t e d . n o t e 2 : r e a d b u r s t o f 8 c a n o n l y b e i n t e r r u p t e d b y a n o t h e r r e a d c o m m a n d . r e a d b u r s t i n t e r r u p t i o n b y w r i t e c o m m a n d o r p r e c h a r g e c o m m a n d i s p r o h i b i t e d . n o t e 3 : r e a d b u r s t i n t e r r u p t m u s t o c c u r e x a c t l y t w o c l o c k s a f t e r p r e v i o u s r e a d c o m m a n d . a n y o t h e r r e a d b u r s t i n t e r r u p t t i m i n g s a r e p r o h i b i t e d . n o t e 4 : r e a d b u r s t i n t e r r u p t i o n i s a l l o w e d t o a n y b a n k i n s i d e d r a m . n o t e 5 : r e a d b u r s t w i t h a u t o p r e c h a r g e e n a b l e d i s n o t a l l o w e d t o i n t e r r u p t . n o t e 6 : r e a d b u r s t i n t e r r u p t i o n i s a l l o w e d b y a n o t h e r r e a d w i t h a u t o p r e c h a r g e c o m m a n d . n o t e 7 : a l l c o m m a n d t i m i n g s a r e r e f e r e n c e d t o b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r . t h e y a r e n o t r e f e r e n c e d t o a c t u a l b u r s t . f o r e x a m p l e , m i n i m u m r e a d t o p r e c h a r g e t i m i n g i s a l + b l / 2 w h e r e b l i s t h e b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r a n d n o t t h e a c t u a l b u r s t ( w h i c h i s s h o r t e r b e c a u s e o f i n t e r r u p t ) . d q s # d q d q s t d q s h t w p r e d q s d m t d q s l t w p s l v i l ( a c ) v i h ( a c ) d d v i l ( d c ) v i h ( d c ) d d d m i n d m i n d q s # d m i n v i h ( a c ) v i l ( a c ) d m i n v i h ( d c ) v i l ( d c ) t d s t d s t d h t d h
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 40 rev . 1.1 april. /2012 figure 25. burst write operation: rl=3 (al=0, cl=3), wl=2, bl=4 c k # c k t d q s s c m d c a s e 1 : w i t h t d q s s ( m a x ) > = t w r t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t n p o s t e d c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e t d s s t d q s s t d s s c o m p l e t i o n o f t h e b u r s t w r i t e w l = r l - 1 = 4 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # > = t w r w l = r l - 1 = 4 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # t d q s s t d s h t d q s s t d s h c a s e 2 : w i t h t d q s s ( m i n ) d q s d q s c k # c k < = t d q s s c m d > = t w r t 0 t 1 t 2 t 3 t 4 t 5 t m t m + 1 t n w r i t e a n o p n o p n o p n o p n o p p r e c h a r g e n o p b a n k a a c t i v a t e c o m p l e t i o n o f t h e b u r s t w r i t e w l = r l - 1 = 2 d n a 0 d n a 1 d n a 2 d n a 3 d q s d q s # d q s > = t r p
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 41 rev . 1.1 april. /2012 figure 26. burst write followed by burst read: rl=5 (al=2, cl=3, wl=4, t wtr =2, bl=4) figu re 27. seamless burst write operation rl=5, wl=4, bl=4 figure 28. write burst interrupt timing: (cl=3, al=0, rl=3, wl=2, bl=8) c k # c k c k e t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 9 t 2 t 3 n o p n o p n o p n o p p o s t c a s # r e a d a n o p n o p n o p n o p d q s a l = 2 d q s # w l = r l - 1 = 4 d q s # d q s c l = 3 r l = 5 > = t w t r d n a 0 d n a 1 d n a 2 d n a 3 d o u t a 0 d q n o t e : t h e m i n i m u m n u m b e r o f c l o c k f r o m t h e b u r s t w r i t e c o m m a n d t o t h e b u r s t r e a d c o m m a n d i s [ c l - 1 + b l / 2 + t w t r ] . t h i s t w t r i s n o t a w r i t e r e c o v e r y t i m e ( t w r ) b u t t h e t i m e r e q u i r e d t o t r a n s f e r t h e 4 b i t w r i t e d a t a f r o m t h e i n p u t b u f f e r i n t o s e n s e a m p l i f i e r s i n t h e a r r a y . t w t r i s d e f i n e d i n t h e t i m i n g p a r a m e t e r t a b l e o f t h i s s t a n d a r d . w r i t e t o r e a d = c l - 1 + b l / 2 + t w t r c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # w r i t e a n o p p o s t c a s # w r i t e b n o p n o p n o p n o p n o p n o p d q s d q s # w l = r l - 1 = 4 d q s # d q s d n a 0 d n a 1 d n a 2 d n a 3 d q d n b 0 d n b 1 d n b 2 d n b 3 n o t e : t h e s e a m l e s s b u r s t w r i t e o p e r a t i o n i s s u p p o r t e d b y e n a b l i n g a w r i t e c o m m a n d e v e r y o t h e r c l o c k f o r b l = 4 o p e r a t i o n , e v e r y f o u r c l o c k s f o r b l = 8 o p e r a t i o n . t h i s o p e r a t i o n i s a l l o w e d r e g a r d l e s s o f s a m e o r d i f f e r e n t b a n k s a s l o n g a s t h e b a n k s a r e a c t i v a t e d .
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 42 rev . 1.1 april. /2012 figure 29. write data mask c k # c k c m d n o p w r i t e a n o p w r i t e b n o p n o p n o p n o p n o p n o p a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d q s d q s # d q s n o t e 1 : w r i t e b u r s t i n t e r r u p t f u n c t i o n i s o n l y a l l o w e d o n b u r s t o f 8 . b u r s t i n t e r r u p t o f 4 i s p r o h i b i t e d . n o t e 2 : w r i t e b u r s t o f 8 c a n o n l y b e i n t e r r u p t e d b y a n o t h e r w r i t e c o m m a n d . w r i t e b u r s t i n t e r r u p t i o n b y r e a d c o m m a n d o r p r e c h a r g e c o m m a n d i s p r o h i b i t e d . n o t e 3 : w r i t e b u r s t i n t e r r u p t m u s t o c c u r e x a c t l y t w o c l o c k s a f t e r p r e v i o u s w r i t e c o m m a n d . a n y o t h e r w r i t e b u r s t i n t e r r u p t t i m i n g s a r e p r o h i b i t e d . n o t e 4 : w r i t e b u r s t i n t e r r u p t i o n i s a l l o w e d t o a n y b a n k i n s i d e d r a m . n o t e 5 : w r i t e b u r s t w i t h a u t o p r e c h a r g e e n a b l e d i s n o t a l l o w e d t o i n t e r r u p t . n o t e 6 : w r i t e b u r s t i n t e r r u p t i o n i s a l l o w e d b y a n o t h e r w r i t e w i t h a u t o p r e c h a r g e c o m m a n d . n o t e 7 : a l l c o m m a n d t i m i n g s a r e r e f e r e n c e d t o b u r s t l e n g t h s e t i n t h e m o d e r e g i s t e r . t h e y a r e n o t r e f e r e n c e d t o a c t u a l b u r s t . f o r e x a m p l e , m i n i m u m w r i t e t o p r e c h a r g e t i m i n g i s w l + b l / 2 + t w r w h e r e t w r s t a r t s w i t h t h e r i s i n g c l o c k a f t e r t h e u n i n t e r r u p t e d b u r s t e n d a n d n o t f r o m t h e e n d o f a c t u a l b u r s t e n d .
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 43 rev . 1.1 april. /2012 figure 30. burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=4, t rtp Q 2 clocks) d q d q s d m d q s # t d s v i h ( a c ) v i h ( d c ) v i l ( a c ) v i l ( d c ) t d h t d s v i h ( a c ) v i h ( d c ) v i l ( a c ) v i l ( d c ) t d h c k # c k c o m m a n d d q s d q s # d q w r i t e t w r w l t d q s s t d q s s d m c a s e 2 : m a x t d q s s d q s d q s # d q d m c a s e 1 : m i n t d q s s d a t a m a s k f u n c t i o n , w l = 3 , a l = 0 , b l = 4 s h o w n d a t a m a s k t i m i n g
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 44 rev . 1.1 april. /2012 figure 31. burst read operation followed by precharge: (rl=4, al=1, cl=3, bl=8, t rtp Q 2 clocks) figure 32. burst read operation followed by precharge: (rl=5, al=2, cl=3, b l=4, t rtp Q 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p p r e c h a r g e n o p n o p n o p b a n k a a c t i v e n o p d q s d q s # a l + b l ' / 2 c l k s d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q > = t r p a l = 1 c l = 3 r l = 4 > = t r a s > = t r t p c l = 3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p p r e c h a r g e a n o p n o p n o p d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 1 f i r s t 4 - b i t p r e f e t c h > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 45 rev . 1.1 april. /2012 figure 33. burst read operation followed by precharge: (rl=6, al=2, cl=4, bl=4, t rtp Q 2 clocks) figure 34. burst read operation followed by precharge: (rl=4, al=0, c l=4, bl=8, t rtp >2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e n o p d q s d q s # r l = 5 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 2 > = t r a s > = t r p c l = 3 > = t r t p c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e n o p d q s d q s # r l = 6 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 4 a l = 2 > = t r a s > = t r p c l = 4 > = t r t p
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 46 rev . 1.1 april. /2012 figure 35. burst write operation followed by precharge: wl= (rl - 1) =3 figure 36. burst write followed by precharge: wl= (rl - 1) =4 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p p r e c h a r g e a n o p n o p b a n k a a c t i v a t e d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + 2 + m a x ( t r t p , 2 t c k ) * c l = 4 a l = 0 f i r s t 4 - b i t p r e f e t c h > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 > = t r p > = t r a s * : r o u n d e d t o n e x t i n t e g e r . c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e a d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s > = t w r w l = 3 c o m p l e t i o n o f t h e b u r s t w r i t e
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 47 rev . 1.1 april. /2012 figure 37. burst read operation with auto precharge: (rl=4,al=1, cl=3, bl=8, t rtp Q 2 clocks) figure 38. burst read operation with auto precharge: (rl=4, al=1, cl=3, bl=4, t rtp >2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 9 t 2 t 3 p o s t c a s # w r i t e a n o p n o p n o p n o p n o p n o p n o p p r e c h a r g e a d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s > = t w r w l = 4 c o m p l e t i o n o f t h e b u r s t w r i t e c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e d q s d q s # r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a l + b l / 2 c l k s c l = 3 a l = 1 a u t o p r e c h a r g e > = t r t p s e c o n d 4 - b i t p r e f e t c h d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 > = t r p t r t p p r e c h a r g e b e g i n s h e r e f i r s t 4 - b i t p r e f e t c h
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 48 rev . 1.1 april. /2012 figure 39. burst read operation with auto precharge followed by activation to the same bank (t rc limit): rl=5(al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) figure 40. burst read operation with auto pre charge followed by an activation to the same bank (t rp limit): (rl=5 (al=2, cl=3, internal t rcd =3, bl=4, t rtp Q 2 clocks) c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e n o p d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 a u t o p r e c h a r g e > = a l + t r t p + t r p a l = 1 r l = 4 t r t p t r p f i r s t 4 - b i t p r e f e t c h p r e c h a r g e b e g i n s h e r e c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 > = t r a s ( m i n ) a l = 2 r l = 5 > = t r c c l = 3 a 1 0 = 1 a u t o p r e c h a r g e b e g i n s > = t r p
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 49 rev . 1.1 april. /2012 figure 41. burst write with auto - precharge (t rc limit): wl=2, wr=2, bl=4, t rp =3 c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t 8 t 2 t 3 p o s t c a s # r e a d a n o p n o p n o p n o p n o p n o p b a n k a a c t i v a t e n o p d q s d q s # d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s c l = 3 > = t r a s ( m i n ) a l = 2 r l = 5 > = t r c c l = 3 a 1 0 = 1 a u t o p r e c h a r g e b e g i n s > = t r p c k # c k c m d t 0 t 1 t 4 t 5 t 6 t 7 t m t 2 t 3 p o s t c a s # w r a b a n k a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v e d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s a u t o p r e c h a r g e b e g i n s w l = r l - 1 = 2 c o m p l e t i o n o f t h e b u r s t w r i t e a 1 0 = 1 > = w r > = t r p > = t r c
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 50 rev . 1.1 april. /2012 figure 42. burst write with auto - precharge (wr+t rp ): wl=4, wr=2, bl=4, t rp =3 figure 43. refresh command figure 44. self refresh operation c k # c k c m d t 0 t 3 t 6 t 7 t 8 t 9 t 1 2 t 4 t 5 p o s t c a s # w r a b a n k a n o p n o p n o p n o p n o p n o p n o p b a n k a a c t i v e d q s d q s # d n a 0 d n a 1 d n a 2 d n a 3 d q ' s a u t o p r e c h a r g e b e g i n s w l = r l - 1 = 4 c o m p l e t i o n o f t h e b u r s t w r i t e a 1 0 = 1 > = w r > = t r p > = t r c c k # c k c k e t 0 t 1 t m t n t n + 1 t 2 t 3 p r e c h a r g e n o p n o p r e f r e f n o p a n y c m d h i g h > = t r p > = t r f c > = t r f c
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 51 rev . 1.1 april. /2012 figure 45. basic power down entry and exit timing diagram figure 46. cke intensive environment figure 47. cke intensive environment c k # c k c k e t 0 t 1 t 5 t m t 2 t 3 c m d > = t x s n r t r p * t c h t c l t c k t 4 t 6 t n > = t x s r d t i s v i l ( a c ) v i h ( a c ) t i s n o p s e l f r e f r e s h o d t t a o f d t i s v i l ( a c ) t i h t i s t i h t i s t i h v i l ( d c ) v i l ( a c ) v i h ( a c ) v i h ( d c ) n o p n o p v a l i d n o t e 1 d e v i c e m u s t b e i n t h e " a l l b a n k s i d l e " s t a t e p r i o r t o e n t e r i n g s e l f r e f r e s h m o d e . n o t e 2 o d t m u s t b e t u r n e d o f f t a o f d b e f o r e e n t e r i n g s e l f r e f r e s h m o d e , a n d c a n b e t u r n e d o n a g a i n w h e n t x s r d t i m i n g i s s a t i s f i e d . n o t e 3 t x s r d i s a p p l i e d f o r r e a d o r a r e a d w i t h a u t o p r e c h a r g e c o m m a n d . t x s n r i s a p p l i e d f o r a n y c o m m a n d e x c e p t a r e a d o r a r e a d w i t h a u t o p r e c h a r g e c o m m a n d . c k # c k c o m m a n d c k e v a l i d t i h t c k e m i n t i h t i h t i h t i s t i s t i s n o p n o p n o p v a l i d v a l i d o r n o p t x p , t x a r d t x a r d s t c k e ( m i n ) e x i t p o w e r - d o w n m o d e d o n ' t c a r e e n t e r p o w e r - d o w n m o d e c k # c k e t c k e n o t e : d r a m g u a r a n t e e s a l l a c a n d d c t i m i n g & v o l t a g e s p e c i f i c a t i o n s a n d p r o p e r d l l o p e r a t i o n w i t h i n t e n s i v e c k e o p e r a t i o n c k t c k e t c k e t c k e
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 52 rev . 1.1 april. /2012 figure 48. r ead to power - down entry figure 49. read with autoprecharge to power - down entry c k # c k e t c k e n o t e : t h e p a t t e r n s h o w n a b o v e c a n r e p e a t o v e r a l o n g p e r i o d o f t i m e . w i t h t h i s p a t t e r n , d r a m g u a r a n t e e s a l l a c a n d d c t i m i n g & v o l t a g e s p e c i f i c a t i o n s a n d d l l o p e r a t i o n w i t h t e m p e r a t u r e a n d v o l t a g e d r i f t c k t c k e t c k e t c k e t x p t x p t r e f i r e f r e f c m d c k # c m d b l = 4 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l r e a d o p e r a t i o n s t a r t s w i t h a r e a d c o m m a n d a n d d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q c k # c m d b l = 8 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q q q q q
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 53 rev . 1.1 april. /2012 figure 50. write to power - down entry c k # c m d b l = 4 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d a q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q c k # c m d b l = 8 t 0 t 2 t x t x + 1 t x + 2 t x + 3 t x + 4 t x + 5 t x + 6 t x + 7 t 1 t x + 8 t x + 9 r d q a l + c l d q s c k e c k d q s # c k e s h o u l d b e k e p t h i g h u n t i l t h e e n d o f b u r s t o p e r a t i o n t i s q q q d q q q q q p r e a l + b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d p r e s t a r t i n t e r n a l p r e c h a r g e a l + b l / 2 w i t h t r t p = 7 . 5 n s & t r a s m i n s a t i s f i e d
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 54 rev . 1.1 april. /2012 figure 51. wr ite with autoprecharge to power - down entry figure 52. refresh command to power - down entry c k # c m d b l = 4 t 0 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t y t y + 1 t 1 t y + 2 t y + 3 w r q w l d q s c k e c k d q s # t i s q q q d q c k # c m d b l = 8 t 0 t m t m + 1 t m + 2 t m + 3 t m + 4 t m + 5 t x t x + 1 t x + 2 t 1 t x + 3 t x + 4 w r q w l d q s c k e c k d q s # q q q d q q q q q t w t r t i s t w t r c k # c m d b l = 4 t 0 t m t m + 1 t m + 2 t m + 3 t x t x + 1 t x + 2 t x + 3 t x + 4 t 1 t x + 5 t x + 6 w r a q w l d q s c k e c k d q s # t i s q q q d q c k # c m d b l = 8 t 0 t m t m + 1 t m + 2 t m + 3 t m + 4 t m + 5 t x t x + 1 t x + 2 t 1 t x + 3 t x + 4 w r a q w l d q s c k e c k d q s # q q q d q q q q q w r * 1 t i s p r e w r * 1 p r e s t a r t i n t e r n a l p r e c h a r g e * 1 : w r i s p r o g r a m m e d t h r o u g h m r s
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 55 rev . 1.1 april. /2012 figure 53. active command to power - down entry figure 54. precharge/ precharge - all command to power - down entry figure 55. mrs/emrs command to power - down entry figure 56. asynchronous cke low event c k # c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 r e f c k e c k t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a n a u t o - r e f r e s h c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 a c t c k e t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a n a c t i v e c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 p r o r p r a c k e t i s t 1 1 c k e c a n g o t o l o w o n e c l o c k a f t e r a p r e c h a r g e o r p r e c h a r g e a l l c o m m a n d c m d t 0 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 m r s o r e m r s c k e t i s t 1 1 t m r d
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 56 rev . 1.1 april. /2012 figure 57. clock frequency chang e in precharge power down mode figure 58. 84 - ball fbga package outline drawing information c k # c k c k e t c k t d e l a y c k e a s y n c h r o n o u s l y d r o p s l o w c l o c k s c a n b e t u r n e d o f f a f t e r t h i s p o i n t t i s s t a b l e c l o c k s c k # c m d t 0 t 2 t 4 t x t x + 1 t y t y + 1 t y + 2 t y + 3 t y + 4 t 1 t z f r e q u e n c y c h a n g e o c c u r s h e r e t r p c k e o d t c k n o p n o p n o p n o p d l l r e s e t n o p v a l i d 2 0 0 c l o c k s t a o f d m i n i m u m 2 c l o c k s r e q u i r e d b e f o r e c h a n g i n g f r e q u e n c y s t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t t x p t i s t i s t i h o d t i s o f f d u r i n g d l l r e s e t
as4c 64 m 16d2 alliance memory inc. reserves the right to change products or specification without notice. 57 rev . 1.1 april. /2012 symbol dimension in inch dimension in mm min nom max min nom max a -- -- 0.0 47 -- -- 1.20 a1 0.010 -- 0.016 0.25 -- 0.40 a2 0.030 0.031 0.033 0.75 0.80 0.85 a3 0.005 0.006 0.007 0.125 0.155 0.185 d 0.311 0.315 0.319 7.9 8.0 8.1 e 0.488 0.492 0.496 12.4 12.5 12.6 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.441 -- -- 11.2 -- f -- 0.12 6 -- -- 3.2 -- e -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 d2 -- -- 0.081 -- -- 2.05 top view bottom view side view pin a1 index detail : "a"

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